% Control % % select7: PC load % % select6: ACC latch % % select5: ALU latch % % select4: PC count up or load enable % % select3: IR latch % % select2: memory read/write % % select1: ACC data select from ALU or memory % % select0: address select PC(1) or IR_L(0) %
ss.clk = s_clk.q; ss.reset = reset; TABLE ss, ir[7..5].q, c, z => select[7..0], ss, fe; s0, B"XXX", X, X => B"00001001", s1, 1; s1, B"XXX", X, X => B"00010000", s2, 0; s2, B"0XX", X, X => B"00100000", s3, 0; s3, B"0XX", X, X => B"01000010", s0, 1; s2, B"100", X, X => B"01000000", s0, 1; s2, B"101", X, X => B"00100000", s3, 0; s3, B"101", X, X => B"00000110", s0, 1; s2, B"110", 0, X => B"00000000", s0, 1; s2, B"110", 1, X => B"10010000", s0, 1; s2, B"111", X, 0 => B"10010000", s0, 1; s2, B"111", X, 1 => B"00000000", s0, 1; END TABLE;
CASE select[2..1] IS WHEN 0 => acc[].d = mem_out[]; % ACC & IR read from memory % WHEN 1 => acc[].d = alu[].q; % ACC read from ALU % WHEN 2 => mem_in[] = alu[].q; % ALU write to memory % WHEN 3 => mem_in[] = alu[].q; % ALU write to memory % END CASE;
% Memory % mem[].clk = t_clk.q; out_port[].clk = t_clk.q; ir[].d=mem_out[]; CASE a_bus[] IS % ROM section % WHEN 0 => mem_out[] = H"84"; WHEN 1 => mem_out[] = H"05"; WHEN 2 => mem_out[] = H"BF"; WHEN 3 => mem_out[] = H"FF"; WHEN 4 => mem_out[] = H"01"; WHEN 5 => mem_out[] = H"02"; % RAM section % WHEN 6 => mem[7..0].d = mem_in[]; mem[7..0].ena = select[2]; mem_out[] = mem[7..0].q; % Input / Output prot % WHEN 30 => mem_out[] = in_port[]; WHEN 31 => out_port[].d = mem_in[]; out_port[].ena = select[2]; % data fix to FF, when ther addres accessed % WHEN OTHERS =>mem_out[] = H"FF"; END CASE;